Anantharaj Thalaimalai Vanaraj

Anantharaj Thalaimalai Vanaraj have been playing a significant role in creating efficient techniques for non-volatile memory performance improvements towards Solid State Drives (SSDs) catering Client and Enterprise applications. Mr.Anantharaj had devised an approach for localized handling of RAID parity for enterprise SSDs. This approach was awarded a US Patent on 16th MAY 2017 (USPTO#9,652,175) as lead inventor. Another method, Mr.Anantharaj had proposed for ONFI protocol based multi-segmented data transfer awarded two US Patents as lead inventor - namely USPTO#9,772,796 on 26th SEP 2017 and USPTO#9,645,765 on 9th MAY 2017. Further Mr.Anantharaj played a key role in a method for reducing data write duplicity in the non-volatile memory which was awarded a US patent (USPTO#10,319,445) on 11th JUN 2019 as second inventor. Another of my proposals on memory logic to handle cross temperature data was awarded a US patent (USPTO#110,535,383) on 14th JAN 2020 as lead inventor. Collaboratively Mr.Anantharaj had supported a method for suspending and resume of an ongoing read operation which was awarded a US patent (USPTO#10,922,013) on 16th FEB 2021 as third inventor.  These patents received more than 100 citations as they were referenced by storage industry stalwarts like Micron technology, KIOXIA Corporation, IBM Corporation and Seagate Technology.

People Leadership:

In 2016, SanDisk-NAND Memory Design group decided to build an independent memory design group at Bangalore, India to develop NAND Memory independent of teams @ HQ. As a seasoned Senior level Manager at India, Mr.Anantharaj was tasked with building a full-fledged logic design, verification and modeling group at  Bangalore, India with an annual budget of one million USD. Mr.Anantharaj have designed a five-step approach to achieve this goal. 

First: selective university hiring targeting reputed Indian universities like IITs & NITs over a period of 2 years. 

Second: Onboard external experienced technical leads/middle level managers (upto 8 years of experience). 

Third: Awarded internships to all campus hired new college graduates with dedicated internal SanDisk mentor

Four: New hire trainings on NAND Memory design by SanDisk experts (USA, Japan or India) for 2 months. 

Five: New hires projects for 3-months (related to their functional domain) along with a project mentor. 

At the end of 2018, Mr.Anantharaj had successfully established a design group of 35 engineers at Bangalore Centre. On the 29th of JUNE 2018, Mr.Anantharaj was promoted to DIRECTOR (R&D Engineering) owing to these key accomplishments.

Collaborative Leadership:

By 2019, the Management of Kioxia Corporation (Formerly Toshiba Memory Corporation) and Western Digital Corporation (Formerly SanDisk) decided to achieve the collaboration of Memory logic Verification. Mr.Anantharaj had led the memory verification task force towards full collaboration within 2 years. Mr.Anantharaj had defined the key collaboration objectives, process and metrics of memory verification platforms. Mr.Anantharaj had driven monthly collaboration meetings in the year 2019 and two verification summits in the years 2019 & 2020. With this dedicated collaboration, Mr.Anantharaj was able to successfully establish very first unified verification platform for 3D NAND Memory projects resulting in ~20% project efforts reduction in more than four 3D NAND Memory product developments. Mr.Anantharaj was recognized in the worldwide All Hands Meet in the year 2021 for his critical leadership role in this joint venture.

innovation on Memory Design Verification:

During Feb 2018, Mr.Anantharaj proposed and implemented Assertion Verification Packages (AVPs) based on IEEE 1800 standard System Verilog Assertions (SVA) towards reusability and portability. This AVP verification strategy led to ~65% reusability and ~80% portability resulting in cost savins of ~ 75k USD per product. Towards addressing memory design bug escapes at System level in Aug 2020, Mr.Anantharaj devised an approach to automate mnemonic based system firmware memory sequences for Pre-Silicon and Post-Silicon platforms. This system sequence automation approach resulted in ~15% cost savings across WD Black and Blue SSD product lines (approx. 200k USD per project). Mr.Anantharaj’s innovative ideas resulted in eighteen trade secrets from Western Digital Corporation which were actively deployed and utilized by SanDisk/Western Digital and KIOXIA Corporation.